RTL refers to the register transfer level representation of a program necessary to implement it in logic.Įarly development on C to HDL was done by Ian Page, Charles Sweeney and colleagues at Oxford University in the 1990s who developed the Handel-C language. However, system design and functional verification in a hardware description language can be tedious and time-consuming, so systems engineers often write critical modules in HDL and other modules in a high-level language and synthesize these into HDL through C to HDL or high-level synthesis tools.Ĭ to RTL is another name for this methodology. Compared to software, equivalent designs in hardware consume less power (yielding higher performance per watt) and execute faster with lower latency, more parallelism and higher throughput. The converted code can then be synthesized and translated into a hardware device such as a field-programmable gate array. Conversion of C-like programs into hardware description languagesĬ to HDL tools convert C language or C-like computer code into a hardware description language (HDL) such as VHDL or Verilog.
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